Silicon solar cells require effective surface passivation to ensure high operating voltages and therefore high energy conversion efficiencies. Surface passivation is usually achieved by depositing or thermally growing a dielectric layer which can either reduce the density of defect states at the surface or largely repel electrical carriers of one polarity from the surface to decrease the probability of carrier recombination at the semiconductor surface.
Thermally-grown layers of silicon dioxide and silicon nitride, the latter deposited by plasma enhanced chemical vapour deposition (PECVD), are commonly-used in solar cell manufacturing as passivation dielectrics. These layers can improve the surface passivation of n-type silicon by storing positive charges, which induce accumulation layers of majority carrier electrons at the semiconductor surface.
Similarly, aluminium oxide layers which can be deposited using either PECVD or atomic layer deposition (ALD), can contain stored negative charges which can effectively passivate p-type silicon surfaces by inducing an accumulation layer of majority carriers.
However, the deposition processes of the abovementioned dielectrics generally require high temperature furnaces or vacuum chambers, which involve a nigh thermal budget and/or long processing periods. Further, chemical and physical vapour deposition processes usually consume source materials that can be hazardous, are expensive and/or toxic and consequently may create environmental problems.
Dielectric layers can be formed on silicon surfaces by anodisation of metal precursor layers in a solution-based electrochemical reaction. The anodisation process has advantages over thermal growth and chemical or physical deposition processes. Typically, the reaction takes place in an electrolytic solution using inexpensive chemicals at room temperature and under atmospheric pressure. Furthermore, the electrochemical bath can be maintained in such a way as to support an inline process with controlled dosing and bleeding of electrolyte to ensure electrolyte stability with time. Quality passivation, however, requires uniform and complete anodisation of the surface layer. Unfortunately, the majority of previously proposed methods for anodising surface layers on semiconductor wafer require the application of a voltage to the layer being anodised whilst the wafer is immersed in an electrolytic solution. This voltage is typically applied using a conductive clip. The voltage is applied to generate an electric field horizontally across the wafer and a lateral current flow through the layer to be anodised. The lateral current can result in a non-uniform anodisation and non-optimal passivation of the device surface. Furthermore, the resistance to the lateral current flow increases with the thickness of the anodised layer, decreasing the anodisation current and increasing processing time.